module Fetch(

  input enable,
  input flush,
  output ready,

//from reg PC
  input [63:0] pc_i,
//to reg PC
  output [63:0] next_pc_o,
  output branch_valid_o,
//memory interface
  input rdata_valid,
  input [31:0] rdata,
  output [63:0] raddr,
  output ren,
//from execute stage
  input [63:0] branch_pc,
  input branch_valid_i,
//to decode stage
  output [63:0] pc_o,
  output [31:0] inst_o,
  output valid_o
);

  wire branch = branch_valid_i;
  wire no_branch = !branch;
  assign next_pc_o = {64{no_branch}}&(pc_i + 64'h4) | {64{branch}}&branch_pc;
  assign branch_valid_o = branch_valid_i;
  assign raddr = pc_i;
  assign pc_o = raddr;
  assign inst_o = rdata;
  assign valid_o = rdata_valid;
  assign ren = enable&(~flush);
  assign ready = enable;
endmodule
